lead DFT Engineers

Key Responsibilities:

• Develop and implement DFT strategies for digital and mixed-signal ICs.
• Insert and validate test structures such as scan chains, boundary scan, and memory BIST.
• Perform ATPG (Automatic Test Pattern Generation) and analyze coverage results.
• Work with design teams to ensure DFT requirements are met.
• Debug and resolve DFT-related issues during silicon bring-up.
• Collaborate with physical design teams to ensure DFT implementation does not impact design performance.
• Develop and maintain DFT methodologies and best practices.
• Provide technical support and guidance to junior engineers.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 4 to 11 years of experience in DFT for digital and/or mixed-signal ICs.
• Proficient in DFT tools such as Mentor Tessent, Synopsys DFTMAX, or Cadence Modus.
• Strong knowledge of scan insertion, ATPG, JTAG, boundary scan, and memory BIST.
• Experience with DFT simulations and fault coverage analysis.
• Familiarity with RTL and gate-level design flows.
• Strong problem-solving skills and attention to detail.
• Excellent communication and teamwork skills.
• Experience with silicon bring-up and debug.
• Knowledge of scripting languages such as Python, Perl, or TCL.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1500.