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Engaged Employer

Quest Global Technologies

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4.0

based on 150 Reviews

999 Quest Global Technologies Jobs

Full Chip Project Lead

Quest Global Technologies

4.0

based on 150 Reviews

5-9 years

Bangalore / Bengaluru

1 vacancy

Full Chip Project Lead

Quest Global Technologies

posted 2mon ago

Job Role Insights

Flexible timing

Key skills for the job

Analytical Chemistry Training Agile Coaching Physical Design Electricals Physical Verification

+ 2 more

Job Description

Quest Global is an organization at the forefront of innovation and one of the world\u2122s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we\u2122re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

Roles & Responsibilities:

Lead the Full chip, Block level activities in the project.
Handson in full chip

Required Skills (Technical Competency):

- 10+ years of professional experience in physical design, preferably with high performance designs.
- Experience inFull Chip Integration activities such as Full Chip Floor Planning,Power Planning , Bus Planning, Full Chip timing, Full Chip Reliability and Full Chip Physical Verification is desirable.
- Experience in leading a team of 6 to 8 PD Engineers is must.
- Good hold on STA and PL/PV activities.
- Experience in automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications.
- Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
- Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
- Versatility with scripts to automate design flow.
- Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
- Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm
- Excellent physical design and timing background.
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.