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SoC Physical Design
HrdWyr Ventures
posted 2mon ago
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Job Description
Job Responsibilities
- SoC Floorplan Development, SoC Padring Integration.
- Perform Physical Synthesis and Optimization, Clock Tree Synthesis and Power Partitioning and Power Distribution Network Planning. Place & Route, Custom placement and routing.
- Timing Closure and Signal Integrity signoff.
- Physical Verification (LVS) and Design Rule Check (DRC).
- Power Integrity Signoff.
- DFM / EM checks.
- Work with Fab for complete Tapeout Process.
Experience and Skills Required
- 5 to 15 years of experience in SoC Physical Design and Chip Integration with complete RTL to GDS flow.
- Expertise in Synthesis, Floor Planning, APR, building Scan Chains, Scan Re- Ordering. Custom Layout, CTS, Parasitic Extraction, Pre / Post Layout Timing Analysis, LVS, DRC, I/O Ring, ESD Integration.
- In-depth understanding of low power, clock and power gating, power partitioning, IR Drop, DFM and EM rules.
- Deep knowledge of Foundry Collateral and experienced in working with fab for Tapeout.
Soft Skills
- Strong analytical, problem-solving, and hands-on skills.
- Self-driven and thrives when facing open-ended tasks.
- Start-up mentality: fast-paced, flexible and team-oriented.
- Good written and verbal communication skills with great documentation skills.
- Flexibility to work with varied schedules and tolerance for ambiguity.
Employment Type: Full Time, Permanent
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