Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC.
Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals.
Perform Functional and Code Coverage Analysis.
Experience and Skills Required
5 to 15 years of experience in IP & SoC Verification.
Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis.
Development of Verification IP and Testbenches.
Experience with AMS simulations desired.
Must have strong debug and analytical capabilities, root cause analysis.
In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models.
Soft Skills
Strong analytical, problem-solving, and hands-on skills.
Self-driven and thrives when facing open-ended tasks.
Start-up mentality: fast-paced, flexible and team-oriented.
Good written and verbal communication skills with great documentation skills.
Flexibility to work with varied schedules and tolerance for ambiguity.