Digital Bench Characterization Engineer, Senior

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOCs (System on Chip) designed by Qualcomm. We work with Design, System, Program Management, Yield, Reliability and Manufacturing teams to Test, support and commercialize Qualcomms products.
As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, clocking architecture, Delay circuits, Power Distribution Network) and High-Speed IO interfaces (PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High-Speed IO IPs and perform failure analysis to root-cause a design problem. You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.

Education Requirements
MTech, BTech or Equivalent in Electronics or Electrical Engineering with 1-3 years of related work experience

Skills/Experience:

Solid understanding of Electronics engineering fundamentals, DDR & High-Speed IO circuit analysis techniques and Semiconductor manufacturing process,

Good understanding of Test and characterization methodology of DDR and High-Speed IO interfaces

In-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).

Hands-on experience using Bench instruments such as oscilloscopes, J-BERT, network / spectrum analyzers, signal generators and Logic analyzers is a must.

Solid software skills for writing and debugging Test code using C, C# or Python. LabView knowledge is a plus.

Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus.

Ability to work effectively in a fast-paced environment with strong verbal and written communication skills.

Keywords

DDR, High-Speed IO, Electrical Spec compliance, Eye Diagram, Jitter, C, C#, Python, LabVIEW

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