STA/Timing Methodology Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Additional About The Role :

Minimum Qualifications:

Bachelor's degree in computer science, Electrical/Electronics' Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Master's degree in computer science, Electrical/Electronics' Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

STA/Timing CAD Methodology Lead

As an STA CAD methodology lead, the role would expect the candidate to lead deployment of new features and or methodologies related to STA and ECO domain

Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few)

There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality.

Key requirements:

Thorough knowledge of the ASIC design cycle and timing closure flow and methodology.

3 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow.

Strong understanding of advanced STA concepts and challenges in advanced nodes

Proficiency scripting languages (TCL, Perl, Python).

Strong background in PNR and Extraction domain.

Experience of constraints development tool (like spyglass) will be added advantage.

Leadership qualities to lead (technically) and manage the STA CAD team

Qualification:

BE/BTech + 2 years of experience, or ME/MTech + 1 years of experience

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