STA Methodology Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

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About The Role ::

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.

Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

Evaluate multiple timing methodologies/tools on different designs and technology nodes.

Work on automation scripts within STA/PD tools for methodology development.

Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

Experience in design automation using TCL/Perl/Python.

Familiar with digital flow design implementation RTL to GDS :ICC, Innovous , PT/Tempus

Familiar with process technology enablement:Circuit simulations using Hspice/FineSim, Monte Carlo.

Candidates with a Bachelor's degree must have 1 to 2 years of relevant experience. Fresh graduates with a Master's degree are also eligible to apply if they have more than 1 year of experience.

Preferred Qualification/Skills

Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

Hands-on experience with STA tools - Prime-time, Tempus

Have experience in driving timing convergence at Chip-level and Hard-Macro level

In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.

Proficient is scripting languages- TCL, Perl, Awk

Basic knowledge of device physics

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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