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Verification Lead
Proxelera
posted 3mon ago
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Fixed timing
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Job Description
- At least 8 years of experience in verification of complex IPs, subsystems, ASICs or SoCs
- Should possess deep knowledge of SystemVerilog with UVM or similar className library, SoC level C/C++ tests and infrastructure
- Should have a proven track record of working in multiple projects in all areas of verification including test planning, coverage definition, test bench creation, regression, report generation and sign-off
- Should be able to partition verification work into multiple independent units, assign them to engineers, provide guidance and deliver with quality and timeliness
Employment Type: Full Time, Permanent
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Strict timing
Monday to Friday
No travel
Day Shift
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