MosChip Technologies - ASIC RTL Design Engineer - System Verilog (5-8 yrs)

MosChip is seeking an ASIC RTL Design Engineer for positions in Bangalore and Hyderabad.

Company overview :

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Experience : 5+ Years.

Notice Period : Immediate joiners (or) 30 days.

Required Skills :

- Experience in Logic design / RTL coding is a must.

- Experience is SoC design and integration for complex SoCs is a must.

- Experience in Verilog/System-Verilog is a must.

- Experience in Multi Clock designs, Asynchronous interface is a must.

- Experience in using the tools in ASIC development such as Lint and CDC.

- Experience in Synthesis / Understanding of timing concepts is a plus.

- Experience in ECO fixes and formal verification.

- Should have knowledge of AMBA protocols AXI, AHB, APB, SoC clocking/reset architecture.

- Excellent oral and written communications skills.

- Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.