PCIe - Design Verification (5+yrs) Hyd/Bangalore

We are looking for Leads and Seniors Exp Min 5 to 10 yrs

Opportunities to work below locations

Hyderabad Bangalore A

USA opportunities for 2025 (5+yrs)

Please share the below details

Cu Ctc:

Exp Ctc:

Notice Period:

Current location:

Preferred Locations:

Skill Set Required

• Strong Familiarity with UVM Verification Methodology
• Any of the following AXI/AHB/CHI/ACE5/GLS/PCIE/C++/CHI/NVME/DDR5/LPDDR5/DDR4/LPDDR4, and peripherals such as USB/PCIe Gen4/5/6/MIPI
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
• Demonstrate the ability to work with cross-functional teams.
• Familiarity with Software development flow including assembly and C or C++ is beneficial