Staff Engineer, Analog Layout

• Perform physical layout for mixed-signal design like high speed ADC, PLLs, Bandgap Voltage Reference, LDO, high speed I/O circuits, general I/Os, ESD structures designs in deep sub-micron CMOS technologies.

• Closely work with circuit designer across different geographies.

• Responsible for floor planning, custom layout design and run physical verifications and sign off for the release.

• Mentoring junior layout engineers.

• As a key member of Marvells Central Engineering team, you will play a leading role on developing next-generation high speed SerDes IPs.

• We work with leading edge finfet technologies to produce best-in- class analog IPs which enable us to move, store, process and secure the worlds data faster and more reliable

What Were Looking For

• Bachelor s or master s Degree and or PhD in Electrical/Electronics Engineering, Microelectronics or related fields with 4 to 8 years of related professional experience.

• Good understanding of advanced semiconductor technology process and device physics.

• Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of the following areas is preferable : Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.

• Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc).

• Experience in advanced technology nodes like 2nm/3nm/5nm is preferable.

• Experience with EMIR analysis, ESD, antenna and related layout solutions.

• Good communication skills and willingness to work with global team.

• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

• Programming skills, automation and circuit Design background is a plus.