Sr. Principal Engineer - DFT

Custom Compute and Storage Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements in CCS BU.

• The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs
• The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space.
• In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs.
• The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test.

• Bachelor s degree in Computer Science, Electrical Engineering or related fields and 18+ years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 16+ years of experience.
• Hands on working experience in various stages of DFT-Execution - SCAN / MBIST / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug
• Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs.
• Strong fundamentals in Digital Circuit Design and Logic Design is required
• Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)
• Prior experience in ASIC design is a plus
• Scripting skills using PERL, Tcl and C-Shell is plus

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