IP Design Verification Engineer

Roles and responsibilities

Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches (BFM, Scoreboard, tests) , and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification

Qualification

Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 10+ years' experience

-OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 8+ years of experience

-OR- PhD degree in Electrical, Electronics, Computer Engineering with 5+ years of experience.

• Mandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving skills .
• Preferred skills :- BFM development , third party VIP integration , evaluation of VIP's , formal verification skills and c++
• Preferred Protocol knowledge on PCIE , Cxl* ,
• Solid verbal/written communication skills.o Effective team player with continuous learning mindset.