Staff Engineer

To work as a timing engineer (STA) and taking care of end to end timing responsibilities for complex SoC projects.

Job Description
In your new role you will:

• Defining and verification of STA constraint for Functional and Test/SCAN Modes.
• Defining PVT s corners required for covering all desired scenarios for a design
• Knowledge on OCV/AOCV/POCV derates.
• Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.
• VASTA timing closure based on chip IR drop.
• Knowledge on signal SI analysis and PT-PX flow.

• Bachelors or Masters in Electrical/Electronics Engineering.
• BE/B.Tech/M.Tech with 6+ years.
• Project leading knowledge is preferred.
• Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations.
• Candidate should have strong STA fundamentals.
• Has done timing sign-off including timing margin calculations. independently, hands-on STA lead of projects.
• Experience in handling STA of multi-power domain designs & constraint mode merging.
• STA flow development, abstraction with bottleneck identification.
• Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs.
• Generate timing ECOs for Physical design.
• Drive ambitious schedules and enables dependent teams to accomplish.
• Interface to design team and PD team and drive TAT reduction for PD.
• Has experience in mentoring junior engineers.
• Proficient with EDA tools from Synopsys/Cadence.
• Excellent analytical & communication skills.
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone.
• Proficient in Tcl and Perl or other scripting relevant language is a plus.

#WeAreIn for driving decarbonization and digitalization.
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