Principal Engineer Infrastructure Package & timing

In your new role you will:

• Define and create padframe /pinning concept for microcontrollerproducts within a team.
• Set targets for timing sign off and support integration teams toachieve timing closure
• Develop Clock reset concepts and transfer the concepts toimplementable solutions
• Ensure that packaging aspects are comprehensively considered in thewhole development process
• Perform quality checks with respective status assessment andreporting using tools like simulators or code checkers.
• Development of new methodologies, service/debugging/bug fixing ofexisting tools and software.

You are best equipped for this task if you have:

• A degree in electrical / electronic /communications engineering,computer science, physics or a related technical field
• Extensive knowledge in Digital Implementation flows Soc integrationpreferred
• Broad knowledge of SoC architecture development needed (incl.Clk/reset concepts, padframe/pinning, timing closure and packaging)
• Detailed knowledge about sub-micron CMOS technologies and experiencein FinFET technologies is a plus
• Excellent communication and coordination skills in English.
• The candidate should be able to work independently, but also beteam-oriented and open to innovative approaches and methods in avolatile environment

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in

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