Staff Engineer verification

Be part of a verification team utilizing leading-edge verificationtools and methodologies to enable the functional verification of large,and complex memory devices.

Job Description
In your new role you will:

• Responsible for Designing self-checking test benches using modern verificationtechniques
• Implementing functional coverage and assertions using System Verilogand UVM.
• Developing TB environment using SV and UVM.
• Developing test and functional coverage plans based on devicespecifications.
• Analyzing and debugging simulation failures, as well as analyzingfunctional coverage results to guarantee zero defect outcomes.

• BE in Electrical Engineering, or equivalent experience
• 7+ years experience in IC verification. Experience withconstrained-random, coverage driven verification environments is a plus.
• Experience in developing the test bench from scratch using SystemVerilog (SV) HDVL and UVM (Universal Verification Methodology).
• Expertise in Gate Level simulations (GLS) and have debugged, rootcaused real netlist issues.
• A solid understanding of verification concepts and experiencedesigning class-based test benches.
• C coding and Power aware simulation will be an advantage
• Excellent written and oral communication skills
• Strong debugging skills , functional simulations and GLS simulations.

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in

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