IIT Hyderabad - Physical Design Engineer - Static Timing Analysis (3-11 yrs)

What You'll Be Doing :

- In this position, you will expect to lead all block/chip level PD activities.

- PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification.

- Work in collaboration with design team for addressing design challenges.

- Help team members in debugging tool/design related issues.

- Constantly look for improvement in RTL2GDS flow to improve PPA.

- Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.

- Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.

Minimum Qualifications :

- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

What We Need To See :

- Strong experience in Physical Design.

- Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.

- Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.

- Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred.

- Well versed with timing constraints, STA and timing closure.

- Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.

- Ability to multi-task and flexibility to work in global environment.

- Good communication skills and strong motivation, Strong analytical & Problem solving skills.

- Proficiency using Perl, Tcl, Make scripting is preferred.

- Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package.