Post Si Validation Tools Developer

Responsibilities

Candidate should have experience in software development role, tools development, firmware development or validation tools development.

Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He will be the key interface on processor Bringup Activities and own key debugs of architecture and micro-architecture issues during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must drive coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on.


Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

Technical Expertise:Very proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++.

Computer Architecture Knowledge:In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification.

Multi-Processor Cache Coherency:Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems.

Operating Systems and Concepts:Atleast 5 years experience with Multithreading, context switching, memory management related development

Preferred technical and professional experience

IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience)

ARM architecture

RISC V architecture

Spike simulator experience, QEMU simulator