Group Tech Lead Design Verification

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.

InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products.

Job Description

InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Group Tech Lead Design Verification to join a growing start up semiconductor development organization and to help drive excellence in our 5G ORAN products.

Key Responsibilities

• Manage a team of 3-5 DV Engineers for technical leadership and mentoring team members with 15+yrs of relevant experience.
• Work as primary interface to US design/verification team members and management.
• Track verification progress, Identify and close verification gaps to show progress towards tape-out.
• Provide executive summary for the verification status on each sub-system.
• Collaborate with cross functional teams (System, Emulation, FW) for silicon tapeout and product solution development.
• Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and debug use-cases.
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
• Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
• Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
• Full-chip functional verification of 5G Digital Radio SOC.
• Develop, review and execute SOC verification plans on internal, and 3rd party Ips.
• Architect verification framework for mix-signal SOC verification.
• Verify full chip SoC using UVM - Directed/Constrained-Random methodology.
• Verify internal and 3rd party IP blocks with functional vector, VIP and UVM.
• Explore and propose advanced verification methodologies - UVM, FPGA prototyping, emulation, etc.

Job Requirements

• M Tech or B Tech degree in Electrical or Computer Engineering or equivalent.
• 15+ yrs of successfully executing and/or managing multiple IP, SOC Verification projects.
• Have successfully led verification efforts at IP and/or SOC level for multiple SOC.
• Extensive experience in developing UVM-based SV test-benches - Directed/Constrained-Random.
• Hands-on experience with CNDS simulation and verification tools (Xcelium, vManager).
• Hands-on experience in 3rd party IP verification using VIPs from CNDS/SNPS with front/back-door loading/configuration.
• Hands-on experience in multi-core ARM CPUs & AXI/AHB/API bus system verification.
• Hands-on experience developing verification collateral in System Verilog and UVM.
• Familiar with Version control software like Git, Subversion.
• Familiar with gate level simulation.
• Familiar with boot rom simulations.
• Familiar with matlab simulations.
• Experience on FPGA emulation.
• Good knowledge of programming language such as C, System-Verilog and scripting language like TCL and Python.
• Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
• Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing.
• Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc).
• Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus.
• Track record of successfully executing block or chip-level verification plans.
• Excellent communication and presentation skills, energetic and self-motivated.
• Work effectively with an off-site/ offshore design and verification teams across locations.

Preferred Skills

• UVM Proficiency is required.
• Knowledge of ARM and Wireless signal-processing design is highly desired.
• Strong communication skills both written and verbal.
• Ambitious and goal oriented.
• Collaborate effectively in a dynamic team environment.

Benefits

• Competitive Salary and stock options
• Learning and development opportunities
• Employer paid health insurance
• Earned, Casual, Sick & Parental leaves.