Group Tech Lead VLSI Design

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.

InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products.

InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Group Tech Lead VLSI Design to join a growing start up semiconductor development organization and to help drive excellence in our 5G ORAN SOC used in 2G/3G/4G-LTE/5G-NR base station products.

Job Requirements:

• Master s and/or bachelor s degree in engineering (or equivalent) in EC/ EE/ CS with 15 or more years of experience in digital SoC development.
• MTech/PhD EE/CS preferred.
• 15 years or more years of experience mixed-signal SoC development required.
• 5+ years of project and team management experience with track record of silicon tape out.
• Hands-on RTL design experiences with Verilog/System Verilog focusing on signal processing HW design such as FIR filter, AGC, FFT/IFFT & etc.
• Thorough understanding of AMBA (AXI, AHB, APB) bus protocol and design requirements.
• Experience in RTL design using Verilog and System Verilog for CPU/control sub-systems (AXI/AHB/APB bus, PCIe, PIPE interface), digital signal processing blocks (FIR filter, FFT/IFFT, NCO) & Analog Serdes block.
• Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers)
• Experience in Gate Level Simulation (GLS) and LEC checking.
• Good understanding on back-end design flow on logic synthesis, constraints, timing analysis, DFT etc.
• Proven knowledge of System Verilog assertions, checkers, and other design verification techniques.
• Knowledge of languages such as C/C++, Perl, Tcl and Python.
• Good verbal and written communication and presentation skills.
• Team player with ability to collaborate with cross-functional teams to resolve issues effectively.

Key Responsibilities

• Manage a team of Design Engineers for technical leadership and mentoring team member for career growth.
• Work as primary interface to US design/verification members and management team.
• Provide executive summary on project tracking, identify and close gaps for the design status.
• Contribute to 5G cellular product specifications and architectures.
• Architect and RTL design on CPU & bus system integration, SERDES PCS/PMA control, Rx/Tx signal processing.
• Participate in design verification to achieve cycle true and bit accurate matching with fix point model.
• Running CDC, LINT, LEC tools for RTL designs.
• Create design constraint file for synthesis.
• Work with PD team for timing closure.
• Work with System, Software, RF, Analog, and Test teams and provide necessary support.
• Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues.
• Participate in SoC specifications reviews and contribute to micro-architecture definitions.
• Front end digital design and implementation - RTL Coding, Lint, CDC, and Synthesis.
• Develop design constraints and coordinate to debug both functional and DFT test issues.
• Supervise/mentor young engineers for task assignment and ensure productivity and quality.
• Project coordination and status update.
• Debug designs, provide timely closure and help to improve SoC design methodologies and verification quality.

Preferred Skills

• Experiences in LTE/5G-NR PHY layer design
• Knowledge on MUMIMO, Beamforming signal processing
• Knowledge of languages such as C/C++, Perl, Tcl and Python.
• Experience with formal verification tools.
• Good knowledge in mixed signal design concepts.
• Ambitious and goal oriented.
• Collaborate effectively in a dynamic team environment.

Benefits

• Competitive salary and stock options.
• Learning and development opportunities.
• Employer paid health Insurance.
• Earned, Casual, Sick & parental leaves