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11 Eximietas Design Jobs

STA Engineer

4-7 years

Bangalore / Bengaluru

1 vacancy

STA Engineer

Eximietas Design

posted 4mon ago

Job Description

  • Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs.
  • Understand Design Architecture and timing requirements
  • Develop timing constraints SDC and validate
  • Work with Physical design to close SDC related timing issues.
  • Analysis of timing from synthesis to verify constraints.
  • Work with architects and logic designers to generate block and full chip timing constraints.
  • Analyse scenarios and margin strategies with Synthesis & Design team.
  • Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints.
  • Work with third party IP, derive timing signoff requirements.
Requirements:
  • Bachelor s or Master s degree in Electrical Engineering or Electronics & Communications.
  • Total 4+ years of experience in STA, timing closure related work.
  • Hands-on experience in ASIC timing constraints generation and timing closure.
  • Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST.
  • Deep understanding and experience in various functional and test modes.
  • Good fundamental on Physical design implementation.
  • Validate timing constraints for Block and Partitions.
  • Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
    Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
  • Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules.
  • Proven ability to lead and mentor junior engineers, fostering their professional growth and development.
Preferred Qualifications:
  • Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
  • Has at least worked on full chip STA closure of large size silicon.
  • Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development.
  • Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration.
  • Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

Employment Type: Full Time, Permanent

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Eximietas Design Benefits

Free Transport
Child care
Gymnasium
Cafeteria
Work From Home
Free Food +6 more
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