SoC Design Verification Engineer

Job Description

Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.Your responsibilities will include but not be limited to:- Validation of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA- Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide- Learning the Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models- Developing debugging tools and software

Qualifications

-Candidate must have either a BS or MS in Computer Science, Computer Engineering or Electrical Engineering.- Extensive Pre-silicon and Post-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others- Proven record of working across validation teams to solve problems- Expert of HW and SW Interaction and debug to root cause- Experience working across validation, architecture, SW, and design teams to resolve debug issues- Minimum 4yrs experience with reading and interpreting technical specs and Register Transfer Level (RTL) code- Minimum 4yrs experience with writing validation plans and software to implement those validation plans- Minimum 4yrs experience with Programming languages/Scripting: C, Perl, Verilog and UNIX or Linux- Minimum 2yrs experience with computer architecture

Preferred Qualifications- 4yrs+ experience with validation or testing experience, especially in a silicon design team- 3yrs+ experience with functional verification environment- 3yrs+ experience with industry standards such as ATB/Coresight, JTAG

Inside this Business Group
The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.