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Design Verification Engineer, Senior Staff
d-Matrix
posted 3mon ago
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Key skills for the job
Job Description
- MS (EE or CS) or equivalent with 5+ Years of relevant experience.
- Experience in SoC verification cycle from architecture to tape out to bring up.
- Good knowledge of verification methodologies such as UVM/OVM etc.
- Hands on ASIC-SoC Design verification tests and debug experience.
- Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
- Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).
- Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).
- Passionate about AI and thriving in a fast-paced and dynamic startup culture.
Preferred:
- Experience with C/C++, SystemC (a big plus!)
- Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.
Employment Type: Full Time, Permanent
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