318 Cost Optimization Jobs

In this position, the candidate will be responsible for designing soft IP cores for Intel's next generation chips for different market segments.

Qualifications

Minimum Qualification

Master of Science (or a Master of Technology) degree in Electrical Engineering with 6 years of relevant industry experience. Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with 8 years of relevant industry experience.

• Relevant ASIC design experience in front end processes including RTL development, Unit verification with assertions.
• Expertise in design, development, and integration of design blocks (IP)
• Expertise in Verilog and system Verilog based logic design
• Experience in synthesis flow and timing closure
• Experience in one/more of the following areas PCI, PCI_Express (RAS), AMBA standards (AXI, AHB, etc..) would prefer
• Knowledge of SVA and associated tools. Jasper, etc
• Knowledge of memory controllers and CPU architecture is a plus
• Looking for highly motivated individuals with the ability to deal with ambiguity
• Knowledge of considerations for performance, power, cost optimization, as well as design integrity for physical implementation is desirable
• Relevant experience in chip design with familiarity with the entire development flow from definition to Tape-Out.
• Good Problem-Solving Ability.
• Ability to work in a team environment.