Senior Logic Design Engineer - RTL/Verilog (12-15 yrs)

Job Description

As a Senior Logic Design Engineer, you will be a key contributor to the development of cutting-edge memory management units (MMUs) for high-performance systems.

You will work closely with a team of talented engineers to design, implement, and verify complex MMU features.

Key Responsibilities :

- Develop and refine microarchitecture specifications for MMU sub-blocks.

- Collaborate with system architects to define the overall MMU architecture.

- Design and implement complex RTL modules for MMU functionality, such as TLB, page table walk, cache coherence, and memory access control.

- Collaborate with physical design teams to optimize the design for timing and area.

- Develop comprehensive verification plans and testbenches.

- Debug design issues and ensure functional correctness.

- Work closely with software, firmware, and verification teams to ensure seamless integration.

Required Skills and Experience :

- Strong understanding of computer architecture, especially memory systems.

- Proficiency in Verilog or VHDL.

- Experience with synthesis and place and route tools.

- Familiarity with verification methodologies (UVM).

- Strong problem-solving and debugging skills.

- Excellent communication and teamwork skills.

- Experience with NuCA/NUMA architectures is a plus