IP Verification Engineer

Key Responsibilities:

• Define overall verification plans with breakdown of Functional, Formal and other Static verification techniques
• Review gaps in overall verification methodology, and work on mitigation steps using new tools, and drive process improvements
• Explore verification methodologies including Formal testbench Acceleration techniques for new generations of IP cores and relevant assertion/constraint/bench ownership
• Develop and maintain verification environments using SystemVerilog, UVM, and Assertion-Based Verification
• Create/enhance testbenches, test cases, and assertions for network IPs
• Collaborate with design engineers to ensure accurate verification of design functionality
• Develop and execute verification plans, test schedules, and functional coverage models

Requirements:

- 6-12 years of experience in verification engineering, with focus on SystemVerilog, UVM, and Assertion-Based Verification
- Proficient in SystemVerilog, UVM
- Experience with assertion-based verification tools (e.g. JASPER, VC_FORMAL)

- Experience in creating test matrix and test plans for IP level verification

- Excellent debugging and problem-solving skills

- Strong communication and teamwork skills

- Possesses good systemverilog/ uvm coding ethics
- Bachelors/Masters degree in Electrical/Computer Engineering or related field

Nice to Have:

- Experience with simulation tools (e.g., VCS, Questa)
- Familiarity with scripting languages (e.g., Python, Perl)
- Knowledge of networking protocols (e.g., IPv4/IPv6, MPLS)