VLSI Design Verification Engineer

1. Design Verification Engineer

Very strong experience on executing IP verification or Subsystem verification of complex blocks

Very strong in SV, UVM, assertions, Testbench, Testplan, coverages etc

Strong experience in verifying Fabric/NOC/Interconnects blocks

Protocol knowledge : AMBA suite (AXI/ACE), PCI-e, CXL, Interrupt handling, Power management

Responsibilities

• Define and help implement the teams design verification methodology.
• Write bus functional models to drive and monitor stimulus.
• Plan and implement block and integration level scoreboards and checkers to verify functional behaviour .
• Write and assess functional coverage, providing input to block level milestones.
• Triage regression failures and identify logic bugs, driving bug closure.
• Provide VLSI-specific expertise to cross-organization projects and programs.
• Mentor less experienced staff members in VLSI design and development innovation.
• Drive VLSI innovation and integration of new technologies into projects.

Requirements

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 4 to 10 years of experience in VLSI design, verification, implementation.
• Expert level knowledge of SV, UVM methodologies, and Protocols like PCIe,Ethernet
• Expert level assessment and problem solving skills.
• Expert level knowledge of designing VLSI components and integrated circuitry.
• Expert level knowledge of programming and scripting, hardware description language, EDA, and/or FPGA tools.
• Experience in executive written and verbal communication skills.