RTL design engineer

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team.

Requirements:
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
4 to 10 years of experience in RTL designs.
Deep knowledge of mixed signal concepts
Deep knowledge of RTL design fundamentals
Deep knowledge of Verilog and System-Verilog
Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Working knowledge of synthesis, static timing, DFT is a huge plus
Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques
Deep knowledge of scripting languages. Perl and Python are plusses
Deep knowledge of Algorithm developments
Synthesis, Checkers, Front-end tools, Scripting languages , Static timing , Verilog Is desirable.