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Design Verification Engineer
Analog Devices
posted 4mon ago
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Flexible timing
Key skills for the job
Job Description
The Engineering Enablement Org is part of the CTO at Analog Devices and is responsible for providing best-in-class tools, flows, methodologies and support to engineering teams across the company to accelerate product development. This position is for an opening in the Systems Verification and Validation (SVV) team within the Engineering Enablement org, focused on the Verification IP Development. Overall, SVV team works to define and promote the adoption of design verification best practices, including Metric-Driven Verification, UVM, Verification IP, DV tools, Formal, FuSa, Security, Portable Stimulus, Emulation and FPGA prototyping technologies.
Job Responsibilities
- Architect, design and develop best-in-class UVM/C based Simulation, Accelerated and Formal Verification IPs for latest generation complex protocols.
- Develop reusable protocol Conformance Test Suite (CTS), Spec annotated Verification plan (vPlan), Portable Stimulus compatible sequences and userguide.
- Integrate VIPs into ADIs UVM Testbench Generator and make it compatible with ADI DV ecosystem.
- As a protocol & VIP expert, support engineering DV teams to adopt in-house and vendor VIPs (including Accelerated VIPs, Formal VIPs), create & deliver protocol training materials, assist in debugging VIP/protocol issues, share learnings at internal and external conferences.
- Explore & apply innovative DV methodologies to improve the existing solutions further.
Job Requirements
- MTech in VLSI/Electronics/Electrical Engineering with 3+ years of relevant industry experience (or) BTech with 5+ years of experience (or equivalent experience).
- Proficient in UVM VIP development and/or IP/Sub-system/SOC verification
- Should have developed complex UVM testbenches from scratch
- Proficient in digital design, digital verification fundamentals, SV, SVA, UVM and MDV.
- Proficient in Python/Perl (C/C++ is a plus)
- Strong analytical, problem-solving and debugging skills
- Highly motivated and team player
- Ability to manage multiple tasks and work effectively in a fast-paced environment
- Excellent communication skills
- Exposure and technical familiarity with commonly used protocols - AMBA, SPI, I2C, etc (JESD, UCIE, ASA is a plus)
- Exposure to hardware emulation platform (Palladium)
- Exposure to Matlab/Simulink
- Exposure to simulators (XLM/VCS etc), Debug solution (Verisium/Verdi), version control software (P4, GIT, etc) and IDE (DVT, etc)
Employment Type: Full Time, Permanent
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What people at Analog Devices are saying
Rating based on 1 Design & Verification Engineer
review
Anonymous · Engineering
in Bengaluru/Bangalore
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Nice work culture
Read 1 reviewDesign & Verification Engineer salary at Analog Devices
reported by
16
employees
₹12
L/yr - ₹35
L/yr
155%
more
than the average Design & Verification Engineer Salary in India
View more details
What Analog Devices employees are saying about work life
based on 87 employees
Flexible timing
Monday to Friday
No travel
Day Shift
Analog Devices Benefits
Cafeteria 
Work From Home 
Gymnasium 
Education Assistance 
Soft Skill Training 
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