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Premium Employer

Advanced Micro Devices

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3.8

based on 254 Reviews

Video summary

219 Advanced Micro Devices Jobs

Sr. Silicon Design Engineer

Advanced Micro Devices, Inc

3.8

based on 254 Reviews

6-11 years

Hyderabad / Secunderabad

1 vacancy

Sr. Silicon Design Engineer

Advanced Micro Devices

posted 21hr ago

Job Role Insights

Flexible timing

Key skills for the job

Social Work Recruitment Analytical Chemistry Silicon Validation Physical Design Static Timing Analysis

+ 2 more

Job Description

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (eg UCIE) to various Business Units/SoCs within AMD.

The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals.

KEY RESPONSIBILITIES:

Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits.

Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability.
Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes.
Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development.
Use scripting skills to meet efficiency and quality goals across all timing workflows.
Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation.
Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics.

PREFERRED EXPERIENCE:

6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs.
Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals.
Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must.
Proficiency in using spice based extraction and simulation tools.
Very good understanding of SOC and Custom flows including physical design and IR drop.

Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies.
Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment.
Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints.