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Premium Employer

Advanced Micro Devices

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3.7

based on 257 Reviews

Video summary

227 Advanced Micro Devices Jobs

SMTS Silicon Design Engineer

Advanced Micro Devices, Inc

3.7

based on 257 Reviews

12-15 years

Hyderabad / Secunderabad

1 vacancy

SMTS Silicon Design Engineer

Advanced Micro Devices

posted 7d ago

Job Role Insights

Flexible timing

Key skills for the job

Electrical Engineering Social Work Recruitment Analytical Chemistry Physical Design Process Simulation

+ 3 more

Job Description

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD.

The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content.

K EY RESPONSIBLITIES :

Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs.

Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY.
Use the performance-power-reliability trade off matrix to achieve IP goals.
Define the appropriate margining methodology and scope for data, clock and async timing paths.
Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes.
Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits.
Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development.
Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes.
Provide technical guidance to junior team members.
Use scripting skills to meet efficiency and quality goals across all timing workflows.

P REFERRED EXPERIENCE :

12+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs.
Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals.
Experience with SerDes or DDR PHY digital logic layer implementation is required.
Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must.
Proficiency in using spice based extraction and simulation tools.
Very good understanding of SOC and Custom flows including physical design and IR drop analysis.
Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued.
Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies.
Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment.
Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints.
Proficient in AMS design flows, tools and methodologies.
Experience in evaluating and adopting new tools and methodologies to improve design processes.