Synopsys Graduate Engineer Trainee (Get) Interview Questions and Answers

3 rounds online, dsa, hr

Q1. Dsa on dp topic
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Q2. Dsa on dp topics
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It was online coding test consist of 2 question
One from DP and other graph

One question of DP within in 45 min time constraints

Q1. Floor value of square root of a number
Ans. 
Floor value of square root of a number is the largest integer less than or equal to the square root.
• The floor value of square root of a number can be found using mathematical functions like floor() or integer division.

• For example, the floor value of square root of 16 is 4, as sqrt(16) = 4.

• For non-perfect square numbers, the floor value of square root can be calculated using approximation methods.
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Level was medium to hard

Q1. Technical interview
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Q2. Questions on DSA Cs fundamentals
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Q3. Coding questions
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Q4. Ques on String array
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Q5. To print tree in anticlock wise direction
Ans. 
To print a tree in anticlockwise direction, start from the bottom left and traverse each level from right to left.
• Start from the bottom left of the tree

• Traverse each level from right to left

• Print the nodes as you traverse
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Some old coding platform with limited testcases

Q1. Normal dp problems
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Q1. About resume and projects
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Q1. About my current company
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Q2. About the work I do in my current company
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Coding round where they ask few coding questions

2 coding questions, aptitude and electronics

Q1. Regarding flip-flops and timers
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Digital electronics, circuits , verilog , asic design flow

Q1. Explain the complete asic design flow process
Ans. 
ASIC design flow process involves steps like specification, design, verification, synthesis, and testing.
• Specification: Define requirements and constraints for the ASIC design.

• Design: Create a high-level design based on the specifications.

• Verification: Verify the design using simulations and tests.

• Synthesis: Convert the design into a netlist of gates and connections.

• Testing: Test the fabricated ASIC to ensure functiona...read more
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Q2. Power reduction techniques in CMOS
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Power reduction techniques in CMOS involve various methods to minimize power consumption in CMOS circuits.
• Use of power gating to selectively turn off power to unused circuit blocks

• Implementing clock gating to disable clock signals to unused circuitry

• Utilizing voltage scaling to reduce power consumption at lower voltages

• Applying dynamic voltage and frequency scaling to adjust voltage and frequency based on workload

• Using...read more
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