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MediaTek India Technology Vlsi Design Engineer Interview Questions and Answers

Updated 4 Apr 2024

MediaTek India Technology Vlsi Design Engineer Interview Experiences

1 interview found

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
6-8 weeks
Result
Selected Selected

I applied via campus placement at National Institute of Technology (NIT), Rourkela and was interviewed before Apr 2023. There were 3 interview rounds.

Round 1 - Coding Test 

C cpp basic and aptitude basic

Round 2 - Group Discussion 

Basics your skills in vlsi and others topic coding

Round 3 - HR 

(5 Questions)

  • Q1. Personal base questions answers
  • Q2. What is your name
  • Q3. About yourself in short
  • Q4. Technical background with skills
  • Q5. About your project in details you have knowlege to your project and coding

Interview Preparation Tips

Interview preparation tips for other job seekers - Try all sections with all sections aptitude technical round

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Toggle the bits of given input
  • Ans. 

    Toggle the bits of given input

    • Create a mask with all bits set to 1

    • XOR the input with the mask to toggle the bits

    • Repeat the process for each bit position

  • Answered by AI
  • Q2. Clear the set bit
Round 2 - Technical 

(2 Questions)

  • Q1. Print the star pattern
  • Ans. 

    Print a star pattern using loops

    • Use nested loops to print the desired pattern

    • Increment the number of stars in each row to create the pattern

    • Example: for a pattern with 5 rows - * , ** , *** , **** , *****

  • Answered by AI
  • Q2. Microprocessor microcontroller topics are asked

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.

Round 1 - Aptitude Test 

Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question

Round 2 - One-on-one 

(3 Questions)

  • Q1. Latches and flip flop all characteristics equation and proof of the characteristics equation in flip flop.applications of flip flop
  • Q2. OOPS,INHERITANCE,VERILOG,BLOCKING - NON BLOCKING ASSIGNMENT OPERATOR and all the basic operations of verilog .
  • Q3. Discussion on work experience.

Interview Preparation Tips

Interview preparation tips for other job seekers - Be bonafide with your fundamentals core of digital circuits and design .
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Amrita Vishwa Vidyapeetham, Amritapuri Campus and was interviewed in Aug 2024. There were 4 interview rounds.

Round 1 - Technical 

(1 Question)

  • Q1. 1st test we have 65 questions focusing on only Opamps
Round 2 - Technical 

(3 Questions)

  • Q1. We have mixed questions 40 in this test
  • Q2. 20 from technical
  • Q3. 20 from aptitude
Round 3 - Technical 

(1 Question)

  • Q1. Asked few questions on network theory based circuits
Round 4 - HR 

(2 Questions)

  • Q1. About the college experience
  • Q2. About family and basic HR questions
Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Write code randc behaviour
  • Ans. 

    randc behavior generates random complex numbers with specified distribution

    • Use randc to generate random complex numbers

    • Specify distribution using arguments like mean, variance, etc.

    • Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2

  • Answered by AI
  • Q2. Functinal coverage
  • Q3. Code coverage related questions
  • Q4. Monitor and scoreboard connections
  • Q5. Project related questions

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to predict if a 32 bit number is divisible by 8, draw a circuit using gates
  • Ans. 

    To predict if a 32 bit number is divisible by 8, design a circuit using gates.

    • Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.

    • If the last three bits are zeros, then the number is divisible by 8.

    • For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.

  • Answered by AI
  • Q2. Various verilog scripting questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Do verilog coding

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. What is cross talk
  • Ans. 

    Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.

    • Occurs when signals from one trace interfere with signals on another trace

    • Can lead to signal distortion or errors in data transmission

    • Prevented by proper spacing and shielding between traces

    • Example: Cross talk between data lines on a PCB causing errors in communication

  • Answered by AI
  • Q2. How to define generated clocks through edges
  • Ans. 

    Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.

    • Specify the source clock for the generated clock

    • Define the edge (rising/falling) on which the generated clock is based

    • Use tools like Synopsys Design Compiler to define generated clocks

  • Answered by AI
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Basics of analog , digital and vlsi
  • Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well on your basics
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Referral and was interviewed before Jan 2022. There were 3 interview rounds.

Round 1 - Coding Test 

Mostly on TB components coding, different scenario coding..

Round 2 - Coding Test 

Mostly on past project experience, different implementation on those projects.

Round 3 - HR 

(2 Questions)

  • Q1. On background details
  • Q2. Reason of job change
  • Ans. 

    Seeking new challenges and growth opportunities in the field of verification engineering.

    • Desire to work on more complex projects

    • Opportunity to learn and apply new technologies

    • Seeking a more collaborative and supportive work environment

    • Career advancement and professional development

    • Company restructuring or downsizing

    • Relocation or commute concerns

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Focus on the verification concepts and past projects.
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Sardar Vallabhbhai National Institute of Technology (NIT), Surat and was interviewed before Jan 2023. There were 2 interview rounds.

Round 1 - Technical 

(2 Questions)

  • Q1. Write a program for an ATM machine to get minimum no. of notes.
  • Ans. 

    Program to calculate minimum number of notes for ATM withdrawal

    • Create an array of available note denominations

    • Sort the array in descending order

    • Initialize a counter variable to keep track of the number of notes

    • Iterate through the array and divide the withdrawal amount by each note denomination

    • Update the counter variable with the quotient

    • Update the withdrawal amount with the remainder

    • Repeat the above steps until the wit...

  • Answered by AI
  • Q2. Can we pass an array to function.
  • Ans. 

    Yes, an array can be passed to a function in embedded firmware programming.

    • Arrays can be passed to functions by specifying the array name as the argument.

    • The function can then access and manipulate the elements of the array.

    • Example: void printArray(int arr[], int size) { ... }

    • Example: int main() { int myArray[] = {1, 2, 3}; printArray(myArray, 3); }

  • Answered by AI
Round 2 - HR 

(1 Question)

  • Q1. What are your salary expectations

Skills evaluated in this interview

MediaTek India Technology Interview FAQs

How many rounds are there in MediaTek India Technology Vlsi Design Engineer interview?
MediaTek India Technology interview process usually has 3 rounds. The most common rounds in the MediaTek India Technology interview process are Coding Test, Group Discussion and HR.
What are the top questions asked in MediaTek India Technology Vlsi Design Engineer interview?

Some of the top questions asked at the MediaTek India Technology Vlsi Design Engineer interview -

  1. Personal base questions answ...read more
  2. Technical background with ski...read more

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