Cadence Design Systems Applications Engineer Interview Questions and Answers

Digital, RC RL circuits, Python, STA

Q1. MOSFET Working, Elmore delay model
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Q2. STA, Switched Capacitor
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Q1. General Questions
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Q2. Projects related qu
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Q1. Mostly heat tranger based, conduction, convection.
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Q2. Coding based question on python list and slicing operation.
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Q1. Cfd based question.
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Q2. Python coding based questions.
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Q1. Proof of Regions of operations of Mosfets in CMOS inverter.
Ans. 
The regions of operation of MOSFETs in a CMOS inverter are cutoff, triode, and saturation.
• MOSFET operates in cutoff region when Vgs < Vth

• MOSFET operates in triode region when Vgs > Vth and Vds < Vgs - Vth

• MOSFET operates in saturation region when Vgs > Vth and Vds > Vgs - Vth

• CMOS inverter uses both NMOS and PMOS transistors to achieve high noise immunity and low power consumption
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Q1. Explain the power leakage and dynamic power in CMOS circuits.
Ans. 
Power leakage is the power dissipated in CMOS circuits when transistors are in off state, while dynamic power is the power dissipated during switching.
• Power leakage occurs due to subthreshold leakage currents in transistors when they are in off state

• Dynamic power is the power dissipated during charging and discharging of capacitive loads in CMOS circuits

• Power leakage increases with decreasing transistor size, while dyn...read more
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Q1. Tell me about your family background
Ans. 
I come from a close-knit family with a diverse background, including engineers, teachers, and entrepreneurs.
• My father is an electrical engineer and my mother is a high school teacher.

• I have a younger sister who is studying business in college.

• My grandparents were entrepreneurs and owned a small business in our hometown.

• Family gatherings are always filled with lively discussions about technology, education, and business
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Q1. Digital related to ff,mux,waveform,fsm
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Q1. Sta max frew ,setup and hold time , numerical questions
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Q1. Fpga architecture,flow ,related to tool ,ram ,fifo
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Q1. Hr question,do you work for longer in this organisation,future goals, willing to relocate
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Q1. FPGA architecture
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Q2. Static Timing Analysis
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Q1. PNR flow and questions related to each stage like floorplanning guidelines, how to do macro placement etc.
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Q2. Challenges you faced in Placement stage, how did you resolve congestion in your design. How to improve timing.
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Q3. CTS spec files, inverters or buffers which is preferable. Skew and latency related questions
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Q4. Detailed discussion about crosstalk, antenna effects and Electromigration
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Q5. Basic TCL scripts to write
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Q1. Focus on Basics of Digital electronics,verilog SV and UVM will be an advantage.Reasoning questions also plays a crucial role.Realizations of gates using and NAND and NOR gate,Realization of gates using mu...read more
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Q2. Don't forget look your projects mentioned in your resume,They will directky ask you to write code,Ask lot of questions on projects,Communication skills willbe added advantage.
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Q3. Reasonig questions:-9 ball's weight checking,horses question,a pond of flowers on which day they full if half fill in 10 days,3L 5L required water 4L,4 pin OTP generation probability with unique numbers,go...read more
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Q4. Don't forget take a look on ypur projects whatever you mentioned in your resume everything matters,Basics of digital electronics,sv and UVM,More focus on practising coding,outputs for snippets plays a cruc...read more
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Q5. One personal advantage for MNC's refferals matters alot,better to ask anyone in linkdin to reffer you.
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