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Kelvin Homes And Furniture Interview Questions and Answers
Q1. Universal Verification Methodology
Universal Verification Methodology (UVM) is a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a standardized way to create testbenches for verifying digital designs.
It helps in improving verification productivity, reusability, and scalability.
UVM consists of a set of classes and macros that help in creating modular and reusable testbenches.
It supports constrained random stimulus generation, functional coverage, and assertion-b...read more
Q2. Coding in verilog
Verilog is a hardware description language used for designing digital circuits.
Verilog is used to describe the behavior of electronic systems.
It is commonly used in the design and verification of digital circuits.
Verilog code consists of modules, which can be instantiated and interconnected to create complex systems.
Simulation tools like ModelSim can be used to test Verilog code before implementation on hardware.
Q3. Task to write 50 transactions to a memory
Writing 50 transactions to a memory task
Use a loop to iterate 50 times and write each transaction to the memory
Ensure each transaction is unique and properly formatted
Verify the transactions after writing them to the memory
Q4. Difference between mealy and moore
Mealy machines have outputs that depend on both present state and input, while Moore machines have outputs that depend only on present state.
Mealy machines have outputs that change asynchronously with input changes
Moore machines have outputs that change synchronously with state changes
Mealy machines have fewer states compared to Moore machines
Example: Traffic light controller is a Mealy machine as the output changes based on both current state and input (traffic conditions)
Ex...read more
Q5. Rtl code for fifo
RTL code for FIFO is a hardware description language code that implements a First-In-First-Out buffer.
Use Verilog or VHDL to write RTL code for FIFO
Define input and output ports for data and control signals
Implement logic for enqueue and dequeue operations
Use registers or memory elements to store data temporarily
Q6. Write a 8X1 mux using if else with clock and reset
Implementing an 8X1 mux using if else statements with clock and reset
Declare input signals, output signal, clock and reset signals
Use if else statements to select the output based on the select lines
Ensure proper handling of clock and reset signals
Example: if(sel == 3) output = in3;
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