Annual salary range
Select experience
₹2.3
Lakhs - ₹2.9
Lakhs
Low Confidence 
Low confidence means that this average salary is based on data that was reported by very few people.
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detailed salary insights 
Average annual salary for most employees Salary comparison with similar companies Estimated monthly take-home salary
Average annual salary for most employees Salary comparison with similar companies Estimated monthly take-home salaryInterested in this particular role?
VLSI Design and Verification Engineer salary at Silicon Interfaces ranges between ₹2.3
Lakhs
to ₹2.9
Lakhs
per year for employees with less than 1 year of experience. Salary
estimates are based on
1 latest salaries received
from various employees of Silicon Interfaces.
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Salary Discussions, Hike & Promotions
2w
a senior consultant
Retention offer
Hello,
Current offer from CG - Total 21.5L, fixed as 19.4 and rest bonus
Retention offer from Deloitte - Total 19.1, fixed as 15.5 and rest bonus (4L)
I understand the offer is less but my manager explained that Deloitte's hikes are better in the market and on an average, I can get 15% every year with good performance.
The same hikes in CG are around 5-6% so financially, my salary growth will definitely be more in Deloitte.
Please give me suggestions. I have good management and projects in Deloitte with WLB but I would like to have some perspective on offered CTC too
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Silicon Interfaces VLSI Design and Verification Engineer Salary FAQs
What is the notice period for VLSI Design and Verification Engineer at Silicon Interfaces in Mumbai?
According to AmbitionBox, 100% of the Silicon Interfaces VLSI Design and Verification Engineers in Mumbai reported a notice period of 15 days or less.This is based on 1 response on AmbitionBox in last 2 years.
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- Silicon Interfaces VLSI Design and Verification Engineer Salaries in Mumbai
Silicon Interfaces VLSI Design and Verification Engineer salary in Mumbai ranges between ₹2.3 Lakhs to ₹2.9 Lakhs. This is an estimate based on latest salaries received from employees of Silicon Interfaces.