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Jisnu Communications FPGA and RTL Design Engineer salaries in Hyderabad / Secunderabad

Annual salary range
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₹3.4 Lakhs - ₹4.4 Lakhs
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Last Updated: 15 Mar 2023

Companies similar to Jisnu Communications for FPGA and RTL Design Engineer in Hyderabad / Secunderabad

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Jisnu Communications FPGA and RTL Design Engineer Salary

2 years exp. (AmbitionBox Estimate)

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₹3.4 L/yr - ₹4.4 L/yr

vs
Company name Avg Annual Salary Open Jobs
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₹8 L/yr - ₹13 L/yr

arrow icon 147% more
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₹4 L/yr - ₹5 L/yr

arrow icon 19% more
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₹3.9 L/yr - ₹4 L/yr

At par
FPGA and RTL Design Engineer salary at Jisnu Communications ranges between ₹3.4 Lakhs to ₹4.4 Lakhs per year for employees with 2 years of experience. Salary estimates are based on 1 latest salaries received from various employees of Jisnu Communications.

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Jisnu Communications FPGA and RTL Design Engineer salary in Hyderabad / Secunderabad ranges between ₹3.4 Lakhs to ₹4.4 Lakhs. This is an estimate based on latest salaries received from employees of Jisnu Communications.