Upload Button Icon Add office photos
filter salariesFilter salaries by

Ffort Raichak FPGA and RTL Design Engineer salaries in India

Annual salary range
Select experience
₹36 Lakhs - ₹46 Lakhs
Low Confidence
info icon
Low confidence means that this average salary is based on data that was reported by very few people.
Salary of majority employees
unlock blur
unlock blur

Interested in this particular role?

Last Updated: 23 Jun 2022

Companies similar to Ffort Raichak for FPGA and RTL Design Engineer

Company name Avg Annual Salary Open Jobs
Logo
HCLTech FPGA and RTL Design Engineer Salary

2 - 8 years exp. (4 salaries)

unlock blur

₹6 L/yr - ₹20.1 L/yr

arrow icon 72% less
Logo
Amazon FPGA and RTL Design Engineer Salary

4 - 5 years exp. (3 salaries)

unlock blur

₹40 L/yr - ₹42 L/yr

arrow icon 1% less
Logo
Intel FPGA and RTL Design Engineer Salary

3 - 8 years exp. (10 salaries)

unlock blur

₹15 L/yr - ₹45 L/yr

arrow icon 38% less
Logo
Amdocs FPGA and RTL Design Engineer Salary

3 - 5 years exp. (9 salaries)

unlock blur

₹19.4 L/yr - ₹40.5 L/yr

arrow icon 22% less
unlock blur

₹4.9 L/yr - ₹17 L/yr

arrow icon 72% less
FPGA and RTL Design Engineer salary at Ffort Raichak ranges between ₹36 Lakhs to ₹46 Lakhs per year. Salary estimates are based on 1 latest salaries received from various employees of Ffort Raichak.

Similar Designation salaries in Ffort Raichak

Senior Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹5.9 L/yr - ₹7.5 L/yr
Junior Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹7.2 L/yr - ₹9.2 L/yr
Senior Software Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹27 L/yr - ₹34.5 L/yr
Deputy Manager Salary
(AmbitionBox Estimate)
unlock blur
₹8.1 L/yr - ₹10.4 L/yr

Salary related reviews for Ffort Raichak

Front office Department

5.0
  •  posted on 31 Oct 2018

3.0
 for  Salary and Benefits

Likes

Is a very Good Place to learn for the freshers but thele is little scope of growth and the quality of Fooding and lodging over there is also very much poor compare to the other hotels

read more
  • Skill development - Excellent
    +3 more

Dislikes

The Fooding and lodging of staffs are poor and unhygienic

  • Promotions - Bad
    +1 more
see more salary related reviews

Tell us how to improve this page.

Ffort Raichak FPGA and RTL Design Engineer salary in India ranges between ₹36 Lakhs to ₹46 Lakhs. This is an estimate based on latest salaries received from employees of Ffort Raichak.