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Aujus Technology

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4.8

based on 3 Reviews

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This rating is based on a small number of reviews, so it may not fully reflect the overall employee experience.
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Aujus Technology FPGA and RTL Design Engineer salaries in New Delhi

Annual salary range
0 - 2 years exp.
₹3.3 Lakhs - ₹4.2 Lakhs
Low Confidence
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Low confidence means that this average salary is based on data that was reported by very few people.
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Last Updated: 22 Jan 2025

FPGA and RTL Design Engineer salary at Aujus Technology ranges between ₹3.3 Lakhs to ₹4.2 Lakhs per year for employees with less than 1 year of experience to 2 years. Salary estimates are based on 2 latest salaries received from various employees of Aujus Technology.

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2w (edited)
a senior quality lead
Offer letter - Accepted
Hi, I'm currently drawing a salary of 27.7 (25.3 is fixed) LPA in my current organization and I got a new offer for 39LPA (33.3 is fixed and 1L joining bonus total 40) I'm almost going to complete by 2 years in my current organization and overall I have 11 years experience as QA. How do you rate this salary jump?
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Aujus Technology FPGA and RTL Design Engineer Salary FAQs

What is the notice period for FPGA and RTL Design Engineer at Aujus Technology in New Delhi?
According to AmbitionBox, 50% of the Aujus Technology FPGA and RTL Design Engineers in New Delhi reported a notice period of 15 days or less, 50% reported a notice period of 1 Month.This is based on 2 responses on AmbitionBox in last 2 years.

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Aujus Technology FPGA and RTL Design Engineer salary in New Delhi ranges between ₹3.3 Lakhs to ₹4.2 Lakhs. This is an estimate based on latest salaries received from employees of Aujus Technology.