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They can remove you any time without even informing you. They just say your performance is not good at all. You are no longer required in this job. Just keep resign asap. Worst company.😤😤😤😤
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Annual salary range
1 - 3 years exp.
₹14.4
Lakhs - ₹18.4
Lakhs
Low Confidence 
Low confidence means that this average salary is based on data that was reported by very few people.
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detailed salary insights 
Average annual salary for most employees Salary comparison with similar companies Estimated monthly take-home salary
Average annual salary for most employees Salary comparison with similar companies Estimated monthly take-home salaryInterested in this particular role?
Companies similar to Altiostar Networks for FPGA and RTL Design Engineer
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 HCLTech FPGA and RTL Design Engineer Salary
2 - 8 years exp. (4 salaries) |  ₹6 L/yr - ₹20.1 L/yr 
29%
less | |
 Intel FPGA and RTL Design Engineer Salary
3 - 8 years exp. (10 salaries) | ₹15 L/yr - ₹45 L/yr 
55%
more | |
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| ||
 Amdocs FPGA and RTL Design Engineer Salary
3 - 5 years exp. (9 salaries) | ₹19.4 L/yr - ₹40.5 L/yr
94%
more | |
 Capgemini Engineering FPGA and RTL Design Engineer Salary
2 - 5 years exp. (5 salaries) | ₹4.9 L/yr - ₹17 L/yr
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 Mistral Solutions FPGA and RTL Design Engineer Salary
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FPGA and RTL Design Engineer salary at Altiostar Networks ranges between ₹14.4
Lakhs
to ₹18.4
Lakhs
per year for employees with experience between 1 year to 3 years. Salary
estimates are based on
2 latest salaries received
from various employees of Altiostar Networks.
Similar Designation salaries in Altiostar Networks
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2w
a product owner
Salary -- Accepted Offer
I accepted an offer where they gave me around 120% hike on current salary, but 2 weeks later I got to know that there are paying other candidates more than me for the same role with even less experience.
Can I reach out to HR for salary revision after accepting offer? I still have 3 weeks left for joining.
*My interview went really well. But HR low balled just becuase of current salary
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Altiostar Networks FPGA and RTL Design Engineer Salary FAQs
What is the notice period for FPGA and RTL Design Engineer at Altiostar Networks?
According to AmbitionBox, 100% of the Altiostar Networks FPGA and RTL Design Engineers reported a notice period of 15 days or less.This is based on 1 response on AmbitionBox in last 2 years.
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- Altiostar Networks FPGA and RTL Design Engineer Salaries
Altiostar Networks FPGA and RTL Design Engineer salary in India ranges between ₹14.4 Lakhs to ₹18.4 Lakhs. This is an estimate based on latest salaries received from employees of Altiostar Networks.