Agasthya App Labs VLSI Design and Verification Engineer Salaries by 3 Employees (Updated 2025)

0 - 2 years exp.

₹4.5 Lakhs - ₹5.8 Lakhs

Low Confidence

Salary of majority employees

28% less than the average VLSI Design and Verification Engineer Salary for 0 - 2 years of experience

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Last Updated: 21 Jul 2024

Companies similar to Agasthya App Labs for VLSI Design and Verification Engineer

Company name	Avg Annual Salary	Open Jobs
Wipro VLSI Design and Verification Engineer Salary 1 - 3 years exp. (32 salaries)	₹3.5 L/yr - ₹6.5 L/yr 14% less
HCLTech VLSI Design and Verification Engineer Salary 0 - 3 years exp. (4 salaries)	₹4.5 L/yr - ₹7.8 L/yr 15% more
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Tech Mahindra VLSI Design and Verification Engineer Salary 2 - 5 years exp. (3 salaries)	₹3.1 L/yr - ₹16 L/yr 77% more
Capgemini VLSI Design and Verification Engineer Salary 0 - 2 years exp. (7 salaries)	₹4 L/yr - ₹4.8 L/yr 11% less
Cerium Systems VLSI Design and Verification Engineer Salary 0 - 3 years exp. (6 salaries)	₹4.1 L/yr - ₹9 L/yr At par

VLSI Design and Verification Engineer salary at Agasthya App Labs ranges between ₹4.5 Lakhs to ₹5.8 Lakhs per year for employees with less than 1 year of experience to 2 years. Salary estimates are based on 3 latest salaries received from various employees of Agasthya App Labs.

Experience wise Agasthya App Labs VLSI Design and Verification Engineer salaries

Last Updated: 21 Jul 2024

Experience	Avg Annual Salary
Fresher (AmbitionBox Estimate)	₹4.5 L/yr - ₹5.8 L/yr
1 year (AmbitionBox Estimate)	₹4.5 L/yr - ₹5.8 L/yr
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2 years (AmbitionBox Estimate)	₹4.5 L/yr - ₹5.8 L/yr

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Salary Negotiation in an interview

Hi, I have had a first round of interview with the company. And mentioned my salary expectations as 15- 20% from my previous LPA. But after that I feel like I have undervalued my expectations. Being in the field for 9 years with the required skill, considering the market and the prospect company is a well known builder, i should have asked more. Anyway a face to face interview is scheduled next week. How to ask them a higher salary from what I have mentioned earlier. And how much I can ask more. Please help. Thanks in advance.

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Agasthya App Labs VLSI Design and Verification Engineer Salary FAQs

What is the notice period for VLSI Design and Verification Engineer at Agasthya App Labs?

According to AmbitionBox, 100% of the Agasthya App Labs VLSI Design and Verification Engineers reported a notice period of 3 Months.This is based on 2 responses on AmbitionBox in last 2 years.

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Agasthya App Labs VLSI Design and Verification Engineer Salaries

Agasthya App Labs VLSI Design and Verification Engineer salary in India ranges between ₹4.5 Lakhs to ₹5.8 Lakhs with an average annual salary of ₹. Salary estimates are based on 3 Agasthya App Labs latest salaries received from various employees of Agasthya App Labs.

Agasthya App Labs VLSI Design and Verification Engineer salaries in India