Technical Manager

15+ years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU/GPU Subsystem or other Mobile SoC Subsystem.

1. In depth understand of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.

2. Creating micro-architecture and detailed design documents for SoC Subsystem design keeping in mind performance, power, area requirements.

3. Strong debugging skills and very good experience in DV tools like Verdi, NCSIM

4. SOC Integration experience preferred of Top Level, Block Level or Subsystem level.

5. Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modeling team.

6. Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis

7. Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc is a must.

8. Understanding and defining constraints and critical high speed path timing closure working with back end teams

Exposure to quality processes in the context of SoC design and verification is an added advantage.

Ability to work in highly competitive consumer SoC design with strict deadlines and quality standards.