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DFT Engineer :: Designer
3-5 years
Bangalore / Bengaluru
1 vacancy
DFT Engineer :: Designer
WebEx
posted 1mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
- Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
- Good understanding of different CTS strategies and providing the feedback to Implementation Team.
- As member of physical design team, drive methodologies and best known methods to streamline and automate physical design work.
- STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
- Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
- Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Good scripting skills (TCL/SHELL/PERL/Python) is a MUST
Who you are:
You are an ASIC engineer with 8+ years of related work experience with a broad mix of technologies including:
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
- Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
- Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.
- Your team will be responsible for Innovative Hardware DFT physical design aspects for new silicon device models, bare die stacked die- driving re-usable test and debug strategies.
- The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight .
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
Employment Type: Full Time, Permanent
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based on 20 employees
Flexible timing
Monday to Friday
No travel
Day Shift
WebEx Benefits
Job Training 
Team Outings 
Education Assistance 
Soft Skill Training 
Health Insurance 
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