IC Design Engineer 4

Block Level and Full chip level Static(IR)/Dynamic(IVD) sign-off
Signal/Power EM sign-off at Block level and Full chip

Custom power grid implementation for block/hardmacs
System level Analysis (PDN) with board, package, interposer and die

Work with SoC and packaging team in bump assignment, pkg routing optimization
Dynamic analysis with vectorless/vectors/mixed mode analysis

PG Grid resistance checks

Knowledge of physical implementation is a plus

Skill Set :

Hands-ons experience in RedHawk/RHSC/Voltus/PDN analysis/3DIC

Good understanding on Power Integrity Signoff Checks

Knowledge of Perl, TCL, Python

Familiarity with Innovus/ICC

Ability to communicate effectively with global cross functional teams

Education

Minimum Qualifications
Bachelors - CS/EE/EC

Work Experiences

Minimum years of experience : 1 to 9 Yrs