Expertise in Analog Layout design Expertise in planner technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Preferred resources with valid regional work permit