Memory Layout Engineer - (TSMC 3nm / 5nm)

Expertise in working on memory layout design for advanced nodes ( TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability
Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness
Expertise in performing debugging of silicon failures and identify layout-related issues
Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler
Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules
Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA)
Provide feedback on circuit designs to improve layout efficiency
Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits)
Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL)
Preferred resources with valid regional work permit

Location: Beijing, Moscow