Physical Design Engineer

1. Chip Floorplanning: Lead or assist in chip floorplanning activities, defining the physical layout of the integrated circuit to meet performance, area, and power goals.
2. Power Distribution Network (PDN) Design: Design and optimize power distribution networks to ensure reliable power delivery across the chip while minimizing IR drops and electromigration effects.
3. Placement and Optimization: Perform block and chip-level placement to meet timing, area, and congestion constraints.
4. Clock Tree Synthesis (CTS): Design and implement clock trees to distribute clock signals across the chip efficiently, minimizing skew and jitter.Role & responsibilities

BSC-Electronics, MSC- electronics

Perks and benefits