Staff Verification Engineer

• As a member of our focused group of HW engineering, the candidate will be involved in verifying a stream processor at IP and block level verification using SV or UVM based environment.
• Should be capable of mentoring the junior team members with technical support.
• Should be involved in close interactions with both RTL design and architecture teams in planning verification environments, test cases, finding and following up on design issues, closing the coverage.
• BE/BTech/ME/MTech in Computer Science or Electronics or Electrical
• Masters/ Bachelors in EE/EC/CS with 5 to 12 years of experience in IP/SoC/ASIC Verification.

REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES

• Should have extensively worked on verifying designs based on RISC/SIMD/VLIW/GPU architecture.
• Should have extensive knowledge in ULT development using UVM/SV, assembly programming and parallel programming.
• Experience in verifying image/video/graphics related Ips is a plus.
• Reviewing and creating test plans Full-chip functional verification on Blaize processor and Test Bench Development in System Verilog targeting complete functionality coverage
• Should be able to come up with test plans along with estimates and risks
• Understanding the processor architecture is a must.
• Strategic planning to meet the organizations goals and to use resources optimally.
• Experience in AMBA AXI, AHB, and APB protocols
• Excellent Test Bench development, debugging and problem-solving skills.

ADDITIONAL SKILLS:

• Knowledge on emulators like Palladium, Zebu a plus
• Knowledge on FPGA Prototyping is a plus.
• Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus.
• Understanding of GPU/AI/ML Processor architecture