Lead DFT Engineer

Role & responsibilities

• Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production.
• Ensure Test Coverage Goals are met at SoC Level.
• Addressing test quality targets in DFT architecture and test pattern generation.
• Leading various aspects of Test architecture including MBIST, Scan & ATPG.
• Work with different functions like front-end design, verification and physical design to ensure production quality silicon.

Specific Knowledge/Skills

• Master/Bachelors Degree in Electrical/Electronic Engineering.
• Experience of 6 to 10 Years in DFT with successful delivery of production quality chips.
• Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST.
• Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
• Self-motivated. Excellent written and verbal communication skill.
• Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
• Should be a team player and willing to work with cross functional teams in issues resolution.

Preferred candidate profile

Perks and benefits