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ASIC Digital Design, Manager
10-20 years
Hyderabad / Secunderabad
1 vacancy
ASIC Digital Design, Manager
Synopsys
posted 2mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- You are responsible for hands-on and also foreseeing the RTL Design, Verification, Architecting Integrating the Subsystems, signing off on the front-end implementation flows, Work with Design and Verification teams driving the life-cycle of the Subsystems from requirement to release phases.
- You are responsible for managing the local teams in Hyderabad, customer communication, requirements-to-deliverables, and on-time delivery of Subsystems.
--- Experience in Managing remote teams, Independently, for a minimum of 4 to 5 years.
--- As a Techno-Manager,
-- knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.
-- Programming skills such as System Verilog, TCL, Perl or Python.
-- The ability to motivate the team and drive innovation.
-- The ability to extract detailed requirements from high-level specification. Foresee the teams work, track progress and drive towards clean-closure.
-- Good communication skills.
As a Manager, this position will require you and your team to :
-- Understand the requirements and Architect the Subsystems based on the requirements.
-- Integrate the RTL and drive the Design tasks to complete the Subsystem.
-- Sign-off on the front-end implementation flows like Synthesis timing closure using Fusion Compiler, SpyGlass CDC/RDC checks, Low Power Architecture, Formality and others.
-- Drive towards Verification closure. Understand the Subsystem requirements/specification and author the Verification Plan. Develop the SV UVM Test Environment
-- Drive the life-cycle of the Subsystems through various phases, from requirements to delivery.
Key Qualifications for this Techno Managerial role :
--- Bachelors or Master s degree in electronics with overall experience of 10+ years.
--- Techno Managerial experience of 4 to 5 years.
--- Hands-on/Lead experience on Subsystems/SOC Design, Architecture and Implementation.
--- Experience with Verilog/System Verilog coding and simulation tools.
--- Experience of implementation flows, namely: synthesis flow, lint, CDC, low power and others.
--- Hands-on/Lead experience on Subsystem Verification.
--- Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components
Employment Type: Full Time, Permanent
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